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Learning from VLSI Design Experience by Weng Fook Lee (English) Hardcover Book
US $155.14
ApproximatelyEUR 139.23
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A new, unread, unused book in perfect condition with no missing or damaged pages. See the seller's listing for full details.
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eBay item number:364699183325
Item specifics
- Condition
- ISBN-13
- 9783030032371
- Type
- NA
- Publication Name
- NA
- ISBN
- 9783030032371
- Book Title
- Learning from Vlsi Design Experience
- Publisher
- Springer International Publishing A&G
- Item Length
- 9.3 in
- Publication Year
- 2019
- Format
- Hardcover
- Language
- English
- Illustrator
- Yes
- Genre
- Computers, Technology & Engineering
- Topic
- Systems Architecture / General, Electronics / Circuits / General, Electronics / General
- Item Weight
- 18.9 Oz
- Item Width
- 6.1 in
- Number of Pages
- Xxix, 214 Pages
About this product
Product Identifiers
Publisher
Springer International Publishing A&G
ISBN-10
303003237X
ISBN-13
9783030032371
eBay Product ID (ePID)
10038516685
Product Key Features
Book Title
Learning from Vlsi Design Experience
Number of Pages
Xxix, 214 Pages
Language
English
Publication Year
2019
Topic
Systems Architecture / General, Electronics / Circuits / General, Electronics / General
Illustrator
Yes
Genre
Computers, Technology & Engineering
Format
Hardcover
Dimensions
Item Weight
18.9 Oz
Item Length
9.3 in
Item Width
6.1 in
Additional Product Features
Number of Volumes
1 vol.
Table Of Content
Chapter 1. Introduction.- Chapter 2. Design Methodology and Flow.- Chapter 3. Multiple Clock Design.- Chapter 4. Latch Inference.- Chapter 5. Design for Test.- Chapter 6. Signed Verilog.- Chapter 7. State Machine.- Chapter 8. RTL Coding Guideline.- Chapter 9. Code Coverage.
Synopsis
This book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.
LC Classification Number
TK7867-7867.5
Item description from the seller
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